Keynote 1: CHIPS NAPMP and CHIPS Metrology Programs

Packaging is evolving from primarily protecting the chip, to complex integration of heterogeneous chiplets. An important aspect of this integration is miniaturization. Substrate feature sizes are shrinking to approach monolithic wiring pitches, the last level via pitches and IP block spacings. Simultaneously, the number and variety of chiplets in the package is increasing to improve performance and functionality. Besides the technology and processes needed to scale down and scale out substrates, there are other difficult issues that need to be addressed: these include power delivery and thermal dissipation, high bandwidth, and potentially active wired, wireless, and photonic connectors to the external world or between subsystems. Finally, to make this vision a reality a chiplet ecosystem needs to be developed with standards that ensure interoperability and cost-effective reuse. Similarly, a comprehensive EDA approach needs to be developed that goes well beyond the electrical abstraction of the system and includes, among other things, thermal and thermomechanical considerations, power delivery, test methodology, metrology, failure analysis, and reliability. The CHIPS NAPMP is developing programs to address these challenges to continue the trend set by Moore’s law through advanced packaging and system integration. As devices become more complex, smaller, and multi-layered, the ability to measure, monitor, predict, and ensure quality in manufacturing becomes much more difficult and uncertain. As greater demands are put on semiconductor device performance and material requirements, these challenges will continue to intensify; the CHIPS Metrology Program is developing research programs to address the highest-priority metrology challenges.

Bio: David A. LaVan is a Program Manager in the CHIPS National Advanced Packaging Manufacturing Program (NAPMP). Before joining CHIPS, he was a group leader in the Material Measurement Laboratory at NIST and has worked on the measurement of thermal and mechanical properties of thin films and devices for almost 30 years. He received his B.S. in Materials Science and Engineering from the University of Florida and his Ph.D. in Mechanical Engineering from the Johns Hopkins University; he was a Postdoctoral Fellow at Sandia National Labs and then in the joint MIT and Harvard HST Program. He was a Co-Chair for the 2018 Fall MRS Meeting and Chair for the 2023 NATAS Meeting. He was named to the National Academies Frontiers of Engineering in 2006 and awarded a Department of Commerce Bronze Medal in 2018.