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Packaging is evolving from primarily protecting the chip, to complex integration of heterogeneous chiplets. An important aspect of this integration is miniaturization. Substrate feature sizes are shrinking to approach monolithic wiring pitches, the last level via pitches and IP block spacings. Simultaneously, the number and variety of chiplets in the package is increasing to improve performance and functionality. Besides the technology and processes needed to scale down and scale out substrates, there are other difficult issues that need to be addressed: these include power delivery and thermal dissipation, high bandwidth, and potentially active wired, wireless, and photonic connectors to the external world or between subsystems. Finally, to make this vision a reality a chiplet ecosystem needs to be developed with standards that ensure interoperability and cost-effective reuse. Similarly, a comprehensive EDA approach needs to be developed that goes well beyond the electrical abstraction of the system and includes, among other things, thermal and thermomechanical considerations, power delivery, test methodology, metrology, failure analysis, and reliability. The CHIPS NAPMP is developing programs to address these challenges to continue the trend set by Moore’s law through advanced packaging and system integration. As devices become more complex, smaller, and multi-layered, the ability to measure, monitor, predict, and ensure quality in manufacturing becomes much more difficult and uncertain. As greater demands are put on semiconductor device performance and material requirements, these challenges will continue to intensify; the CHIPS Metrology Program is developing research programs to address the highest-priority metrology challenges.

Bio: David A. LaVan is a Program Manager in the CHIPS National Advanced Packaging Manufacturing Program (NAPMP). Before joining CHIPS, he was a group leader in the Material Measurement Laboratory at NIST and has worked on the measurement of thermal and mechanical properties of thin films and devices for almost 30 years. He received his B.S. in Materials Science and Engineering from the University of Florida and his Ph.D. in Mechanical Engineering from the Johns Hopkins University; he was a Postdoctoral Fellow at Sandia National Labs and then in the joint MIT and Harvard HST Program. He was a Co-Chair for the 2018 Fall MRS Meeting and Chair for the 2023 NATAS Meeting. He was named to the National Academies Frontiers of Engineering in 2006 and awarded a Department of Commerce Bronze Medal in 2018.

Dr. Suresh K. Sitaram

Dr. Suresh K. Sitaraman is a Regents’ Professor and a Morris M. Bryan, Jr. endowed Professor in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology (Georgia Tech). Dr. Sitaraman is the Director for the Flexible and Wearable Electronics Advanced Research (FlexWEAR@Tech) Program and the Director for the Computer-Aided Simulation of Packaging Reliability (CASPaR) Lab at Georgia Tech. His expertise is in the areas of fabrication, characterization, physics-based modeling, and thermal-mechanical and reliable design of nano-scale and micro-scale structures for a wide range of applications. Dr. Sitaraman has co-authored more than 340 journal and conference publications in these areas. He has managed several research and development projects funded by US federal agencies, industry, and other sources totaling millions of dollars, and has mentored a vast array of post-doctoral fellows as well as doctoral, master’s, bachelor’s, and high-school students. Prior to joining Georgia Tech in 1995, Dr. Sitaraman was with IBM Corp.

Dr. Sitaraman’s work has been recognized through several awards and honors. Among them, he has received a Best Associate Editor award from the IEEE Transactions on Components, Packaging, and Manufacturing Technology (T-CPMT) in 2023, the Zeigler Outstanding Educator Award from Georgia Tech/Mechanical Engineering in 2019, the Outstanding Achievement in Research Program Development Award (Team Leader) from Georgia Tech in 2017 and the ASME/EPPD (Electronic and Photonic Packaging Division) Applied Mechanics Award in 2012. Dr. Sitaraman has received the Sustained Research Award from Georgia Tech – Sigma Xi in 2008 and the Outstanding Faculty Leadership Award for the Development of Graduate Research Assistants, Georgia Tech in 2006. His co-authored papers have won the Commendable Paper Award from IEEE Transactions on Advanced Packaging in 2004 and the Best Paper Award from IEEE Transactions on Components and Packaging Technologies in 2001 and 2000. Dr. Sitaraman has also received the Metro-Atlanta Engineer of the Year in Education Award in 1999 and the NSF-CAREER Award in 1997. Dr. Sitaraman is an ASME Fellow and a NextFlex Fellow.

Dr Suresh Sitaraman received his Doctor of Philosophy (PhD) from The Ohio State University, his Master of Applied Science (M. A. Sc.) degree from the University of Ottawa, Canada and his B. Eng. degree in Mechanical Engineering from the Regional Engineering College, Tiruchirappalli (now known as National Institute of Technology) affiliated with the University of Madras, India. He received the Distinguished Alumnus Award for Excellence in Academic/Research from the National Institute of Technology, Tiruchirappalli in 2014 and the Thomas French Achievement Award for alumni who have distinguished themselves as scholars and educators from the Department of Mechanical and Aerospace Engineering, The Ohio State University in 2012.

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