Dr. Ravi Mahajan
Ravi Mahajan is an Intel Fellow and the Director of Pathfinding for Assembly and Packaging technologies for future silicon nodes. Ravi also represents Intel in academia through research advisory boards, conference leadership and participation in various student initiatives.
Ravi has led Pathfinding efforts to define Package Architectures, Technologies and Assembly Processes for multiple Intel silicon nodes since 2000, spanning 90nm, 65nm, 45nm, 32nm, 22nm and 7nm silicon. Earlier in his Intel career, he spent eight years as a Technologist and manager for the Thermal-Mechanical Tools and Analysis Group. In these roles, Ravi oversaw a Thermal-Mechanical Lab chartered with delivering detailed thermal and mechanical characterization of Intel’s packaging solutions for current and future processors. His group was also responsible for the collaborative development of a number of technologies for the thermal management of micro-electronics, high precision thermal and thermo-mechanical characterization and modeling techniques.
A prolific inventor and recognized expert in microelectronics packaging technologies, Ravi holds more than 50 patents, including the original patents for silicon bridges that became the foundation for Intel’s EMIB technology. His early insights also led to high-performance, cost-effective cooling solutions for high-end microprocessors and the proliferation of photo-mechanics techniques used for thermo-mechanical stress model validation.
Ravi joined Intel in 1992 after earning a bachelor’s degree from Bombay University, a master’s degree from the University of Houston, and a Ph.D. from Lehigh University, all in Mechanical Engineering. His contributions during his Intel career have earned him numerous industry honors, including the SRC’s 2015 Mahboob Khan Outstanding Industry Liaison Award, the 2016 THERMI Award from SEMITHERM, the 2016 Allan Kraus Thermal Management Medal & the 2018 InterPACK Achievement award from ASME and the 2019 “Outstanding Service and Leadership to the IEEE” Awards from IEEE Phoenix Section & Region 6.
He is an IEEE EPS Distinguished Lecturer. He is one of the founding editors for the Intel Assembly and Test Technology Journal (IATTJ) and currently VP of Publications & Managing Editor-in-Chief of the IEEE Transactions of the CPMT. Additionally, he has been long associated with ASME’s InterPACK conference and was Conference Co-Chair of the 2017 Conference. Ravi is a Fellow of two leading societies, ASME and IEEE. He was named an Intel Fellow in 2017.