General Chair: Dr. Madhusudan Iyengar, Google
Technical Program Chair: Dr. Michael Ohadi, University of Maryland
Thermal Management: Chair Thomas Brunschwiler, PhD, IBM Corp; Co-chair Saurabh Shrivastava, PhD, Panduit Corp; Co-chair Mike Ellsworth, IBM Corp.
Mechanics: Chair Kaustubh Nagarkar, General Electric, Jin Yang, Intel, Kaushik Mysore, Advanced Micro Devices, Ricky Lee, Hong Kong University of Science and Technology
Emerging Technologies: Chair Dr. Ashish Gupta, Intel Corporation; Co-Chair: Prof. Amy Marconnet, Purdue University; Co-Chair: Dr. Vadim Gektin, Futurewei Technologies; Co-Chair: Prof. Patrick McCluskey, University of Maryland
Student Poster and Networking Session: Chair: Milnes P David, IBM; Co-chairs: Parisa Foroughi, Dell; Amir Shooshtari, Univ. of Maryland; Jaeho Lee, UC Irvine.
Panels Track: Co-chair Victor Chiriac, Qualcomm; Co-chair Y.C. Lee, University of Colorado;
Tutorials Committee: Dr. Gamal Refai-Ahmed, PhD, GE Global Research; Mehdi Asheghi, PhD, Stanford University
Tech Talk Sessions: Karl Geisler, 3M, and Mike Ellsworth, IBM
Artistic Chair: Disha Bora, Anveshak; Co-chair: Darin Sharar, Army Research Lab
Entertainment & A/V Logistics Chair: Dr. Pritish Parida, IBM.
Sponsorship & Exhibits Committee: Sandeep Tonapi, PhD, Anveshak; Dr. Mehdi Asheghi, Stanford University.
Treasurer: Dustin Demetriou, IBM Corp.
Administration Chair: Paul Wesling, HP (retired)
Publications Chair: Paul Wesling, HP (retired)
The Advance Program is now available for download and review. Please use one of the following links:
Full Advance Program (Version 4.2, May 12, PDF)
Listed below are the titles of the sessions:
THERMAL MANAGEMENT TRACK
EMERGING TECHNOLOGIES TRACK
Professional Development Courses at ITherm/ECTC 2017
(lunch and notes are included)
We invite you to come to Orlando a day early, for your choice of 18 Short Courses on Tuesday, May 27, 2017. Review the titles and world-class instructors below; for topics of interest; click the link to get a full description, or download details on all 18 courses. Then register for ITherm and your choices. If you’re already registered, please add on these classes at low attendee rates.
We especially call your attention to three courses covering the thermal field:
6. INTEGRATED THERMAL PACKAGING AND RELIABILITY OF POWER ELECTRONICS,
taught by Profs. Patrick McCluskey and Avram Bar-Cohen (University of Maryland);
9. THERMO-ELECTRIC COOLERS: CHARACTERIZATION, RELIABILITY, AND MODELING,
taught by Jaime Sanchez (Intel Corporation),
18. THERMO-ELECTRICAL CO-DESIGN OF 3D CHIP STACKS,
taught by Ankur Srivastava and Avram Bar-Cohen (University of Maryland).
You may obtain Continuing Education Units (CEUs) for these courses.
3. LED PACKAGING, SYSTEM, AND RELIABILITY CONSIDERATIONS. Course Leader: Xuejun Fan - Lamar University
4. SYSTEM SCALING FOR NEW ERA OF SELF-DRIVING, INFOTAINING AND ELECTRIC CARS. Course Leaders: Rao Tummala and Venky Sundaram - Georgia Institute of Technology
5. POLYMERS AND NANO-COMPOSITES FOR ELECTRONIC AND PHOTONIC PACKAGING. Course Leaders: C. P. Wong - Georgia Institute of Technology; Daniel Lu - Henkel Corporation
6. INTEGRATED THERMAL PACKAGING AND RELIABILITY OF POWER ELECTRONICS. Course Leaders: Patrick McCluskey and Avram Bar-Cohen - University of Maryland … full details
7. FUNDAMENTALS OF ELECTRICAL DESIGN AND FABRICATION PROCESSES OF INTERPOSERS, INCLUDING THEIR RDLs. Course Leaders: Ivan Ndip and Michael Töpper - Fraunhofer IZM
8. INTRODUCTION TO MECHANICS BASED QUALITY AND RELIABILITY ASSESSMENT METHODOLOGY. Course Leaders: Shubhada Sahasrabudhe and Sandeep Sane - Intel Corporation
9. THERMO-ELECTRIC COOLERS: CHARACTERIZATION, RELIABILITY, AND MODELING. Course Leader: Jaime Sanchez - Intel Corporation … full details
12. OPERATION, DESIGN, CHARACTERISTICS, AND KEY PARAMETERS OF INTEGRATED SILICON ANALOG COMPONENTS. Course Leader: Badih El-Kareh - Consultant
13. DESIGN AND ANALYSIS OF HIGH-PERFORMANCE MEMORY SYSTEMS. Course Leader: Wendem Beyene - Rambus
14. POLYMERS FOR ELECTRONIC PACKAGING. Course Leader: Jeffrey Gotro - InnoCentrix, LLC
15. NOVEL INTERCONNECT AND SYSTEM INTEGRATION TECHNOLOGIES. Course Leader: Muhannad Bakir - Georgia Institute of Technology
16. PACKAGE FAILURE MECHANISMS, RELIABILITY, AND SOLUTIONS. Course Leader: Darvin Edwards - Edwards Enterprises
17. 3D IC INTEGRATION AND 3D IC PACKAGING. Course Leader: John Lau - ASM Pacific Technology Ltd.
18. THERMO-ELECTRICAL CO-DESIGN OF 3D CHIP STACKS. Course Leaders: Ankur Srivastava and Avram Bar-Cohen - University of Maryland … full details
Details on Thermal Courses:
6. INTEGRATED THERMAL PACKAGING AND RELIABILITY OF POWER ELECTRONICS. Course Leaders: Patrick McCluskey and Avram Bar-Cohen - University of Maryland
Power electronics are becoming ubiquitous in engineered systems as they replace traditional ways to control the generation, distribution, and use of energy. They are used in products as diverse as home appliances, cell phone towers, aircraft, wind turbines, radar systems, smart grids, and data centers. This widespread incorporation has resulted in significant improvements in efficiency over previous technologies, but it also has made it essential that the reliability of power electronics be characterized and enhanced. Recently, increased power levels, made possible by new compound semiconductor materials, combined with increased packaging density have led to higher heat densities in power electronic systems, especially inside the switching module, making thermal management more critical to performance and reliability of power electronics. Following a quick review of heat transfer principles and thermal management techniques, along with prognostic health management approaches to assess and ensure reliability, this short course will present the latest developments in the materials (e.g. organic, flexible), packaging, assembly, and thermal management of power electronic modules, MEMS and systems, along with modeling and testing techniques. This course will emphasize thermal packaging techniques capable of addressing performance limits and reliability concerns associated with increased power levels and power density in power electronic components.
9. THERMO-ELECTRIC COOLERS: CHARACTERIZATION, RELIABILITY, AND MODELING. Course Leader: Jaime Sanchez - Intel Corporation
Thermo-electric coolers are devices widely used in the semiconductor industry as the main thermal engines for thermal control during test of integrated circuit devices. They offer the ability to both heat and cool a device under test to mimic worst case platform conditions and defect screening at different temperatures. In this short course, we will review fundamental characterization techniques of thermoelectric coolers that allow the direct measurement of relevant properties such as the effective Seebeck coefficient, electrical resistivity, and thermal impedance. A detailed numerical modeling approach will be discussed that utilizes user-defined functions in Fluent that allows a close representation of these devices matching experimental conditions. Experimentation and numerical analysis techniques will be discussed that enable the full characterization of a thermal solution based on thermoelectric coolers both in steady and transient state. A comprehensive overview of modeling and experimentation techniques will be provided that capture the dynamic behavior of a thermal solution connected to a closed loop control algorithm: the impact of various approaches of controlling the junction temperature of a device under test under different conditions, as well as the sensitivity of the dynamic response of the full system including the effect of active power management of the device under test. Finally, experimental techniques based on reliability statistics will be covered that have a direct application into predicting the life of a thermo-electric cooler under various test conditions.
18. THERMO-ELECTRICAL CO-DESIGN OF 3D CHIP STACKS. Course Leaders: Ankur Srivastava and Avram Bar-Cohen - University of Maryland
3D integration provides significant improvements in device density, interconnect delays, system integration, and computational efficiency but is expected to lead to higher heat densities, along with decreased thermal management access to individual chips and on-chip hotspots. To achieve the inherent computational advantages of 3D integration it will, thus, be necessary to unify the thermal and electrical design of 3D chip stacks and explore new thermal management paradigms for such packaging form factors. This PDC will begin with a brief review of chip packaging, placing 3D chip stacks in the context of packaging history and identifying the form factors and heat dissipation loads expected in homogeneous and heterogeneous 3D integration. Attention will then turn to thermal-electrical "co-design", unifying the circuit layout with the thermal and fluidic aspects of the design to create an integrated co-design environment that enables designers to estimate the impact of the cooling solutions on the electrical aspects and vice versa. Recognizing the growing popularity of FPGAs, especially those which exploit 3D integration, the discussion shall pay attention to the nuances of FPGA design, as well as the more-traditional ASICs. It will be shown that relying on conventional "remote cooling" techniques for 3D integration could have catastrophic consequences, necessitating use of embedded cooling solutions, including integrated micro-fluidics, to achieve the performance goals. The PDC will close with several co-design case studies which demonstrate the potential impact of such a design activity on the performance and energy efficiency of 3D ICs
Continuing Education Units
The IEEE Components, Packaging and Manufacturing Technology Society (CPMT) has been authorized to offer Continuing Education Units (CEUs) by the International Association for Continuing Education and Training (IACET) for all Professional Development Courses that will be presented at the 64th ECTC.
CEUs are recognized by employers for continuing professional development as a formal measure of participation and attendance in "non-credit" self-study courses, tutorials, symposia and workshops. Complete details, including voluntary enrollment forms, will be available at the conference. All costs associated with ECTC Professional Development Courses CEUs will be underwritten by the conference, i.e. there are no additional costs for Professional Development Courses attendees to obtain CEU credit.
To Apply: Please fill out the Student Poster Session Application Form by February 7, 2016.
The student poster and networking session is open to all registered students who have submitted a technical paper, and provides opportunities for them to present their research and interact with other conference attendees from industry and academia. There will also be a networking element that allows interested students to distribute resumes and get connected to industrial representatives.
Interested students can apply for these exciting opportunities using the poster application form, available on the conference website. Students who apply will be competitively selected for poster presentation at the conference and for travel grants.
Outstanding posters will also be selected for awards and will be judged based on technical merit, clarity and self-sufficiency of the content, novelty and originality of the work, overall impact of the poster display, and oral presentation at the poster session. The poster awards are independent of the paper awards and the same work is eligible for winning both awards based on the specific judging criteria for each.
We strongly encourage all students who have or plan to submit technical papers to participate at the Student Poster and Networking Session and to utilize these opportunities to publicize your research and help build your network. We look forward to your posters!
Submission and selection criteria:
To Apply: Please fill out the Student Poster and Networking Session application form.
For further information, please contact the session committee, at email@example.com.